1. Field of the Invention
This invention relates generally to sense amplifiers for semiconductor memory devices, and more particularly to a sense amplifier that employs a current mirror to increase the voltage differential between a reference signal and a sense signal.
2. Description of the Related Art
To increase the integration level of semiconductor memory devices, the size of individual memory cells must be decreased. Such a reduction in memory cell size inevitably results in a reduction in memory cell current. For semiconductor memory devices intended for use in portable electronic equipment which operates at low voltages, the memory cell current required for sensing data is reduced even further because the devices operate at very low voltages.
However, when the current through a semiconductor memory cell is decreased, the speed of a sense amplifier which is used to sense the state of the memory cell decreases in proportion to the decrease in the memory cell current. As a result, the operating speed of the semiconductor memory device is reduced.
A sense amplifier senses and amplifies the voltage difference between an input sense signal, which has a voltage that is determined by the cell current flowing through a memory cell, and a reference signal, which has a voltage that is determined by a reference current which is typically generated by a reference cell.
The speed of a sense amplifier can be increased by increasing the voltage difference between the sense signal and the reference signal. In the case of existing semiconductor memory devices, however, the difference between the sense voltage and the reference voltage is typically small because the devices are operated at low voltages. Many efforts have been made to increase the voltage difference between the sense voltage and reference voltage so as to increase the operating speed of the memory device.
FIG. 1 is a schematic diagram of a prior art sense amplifier. The sense amplifier of FIG. 1 includes a sense voltage signal generator 200 for generating a sense voltage signal at sense node N20 in response to the state of a memory cell. A reference signal generator 100 generates a reference voltage signal at reference node N2. The sensing amplifier also includes a differential amplifier 300 for amplifying the voltage difference between the sense signal and the reference signal.
The reference signal generator 100 includes an inverter comprised of PMOS transistor 101 and NMOS transistor 102 for inverting a control signal/SA. An NMOS transistor 106 has a channel connected in series between a node N1 and power supply ground terminal. The NMOS transistor 106 also has a gate connected to a node N3. The reference signal generator 100 further includes another NMOS transistor 103 having a channel coupled between a power supply terminal and a node N2, and a gate the controls the transistor in response to a pre-charge signal .O slashed.PRE. A PMOS transistor 104 has a channel connected in series between the power supply terminal and node N2. The PMOS transistor 104 also has a gate connected to node N2. Another NMOS transistor 105 has a channel connected in series between the nodes N2 and N3. The NMOS transistor 105 has a gate to which the voltage at the node N1 is applied. The inverter includes a PMOS transistor 101 and an NMOS transistor 102 having channels connected in series between the power supply terminal and the power supply ground terminal. The PMOS transistor 101 and NMOS transistor 102 receive the sense amplifier control signal/AS at their common gate and are driven in response to the control signal.
The sense voltage signal generator 200 has the same configuration as the reference voltage signal generator 100. Specifically, the sensing voltage signal generator 200 includes PMOS transistors 201 and 204 which correspond PMOS transistors 101 and 104, respectively, and NMOS transistors 202, 203, 205 and 206 which correspond to NMOS transistors 102, 103, 105 and 106, respectively, and nodes N10, N20 and N30 which corresponds nodes N1, N2 and N3, respectively.
In operation, when the sense amplifier control signal/SA is switched from the high logic level to the low logic level, PMOS transistor 101 is activated and NMOS transistor 102 is deactivated. This causes the voltage at node N1 to increase to high level. The precharge control signal .O slashed.PRE is switched from low to high simultaneously with the high to low transition of the sense amplifier control signal/SA. This activates NMOS transistor 103, thereby causing the voltage at node N2 to rise.
When the voltages at nodes N1 and N2 increase, current flows from node N2 to N3 by virtue of the activation of NMOS transistor 105. As a result, capacitor C1 is charged, thereby causing the voltage at node N3 to rise. This in turn causes the voltage at the gate of NMOS transistor 106 to rise. The voltage at node N1 is then fixed at a level at which the current supply capability of PMOS transistor 101 is balanced with the current discharge capability of NMOS transistor 106.
After the voltage at node N1 is stabilized at a fixed level, the precharge control signal .O slashed.PRE is deactivated, i.e., switched from high to low, and NMOS transistor 103 stops supply current to node N2. Under this condition, current supply transistor 104 is the only transistor that supplies current to node N2. Since current is discharged from node N2 by a reference current supply source 107 in this state, the voltage at node N2 is determined by the difference between the amount of current supplied by PMOS transistor 104 and the amount of current discharged by the reference current supply 107. This voltage is applied to one input terminal of the differential amplifier 300 as a reference voltage signal. Thus, the reference signal is generated at node N2 by the current source 104 in response to the current demanded by reference current supply source 107.
Since the sense voltage signal generating unit 200 has essentially the same configuration as the reference voltage signal generator 100, the operation is essentially the same except that, when the signal .O slashed.PRE is activated, the voltage at sense node N20 is determined by the difference between the amount of current supplied by PMOS current supply transistor 204 and the amount of current discharged by the memory cell current supply source 207. This voltage is applied to the other input terminal of the differential amplifier 300 as the sense voltage signal.
The reference current supplied by the reference cell current supply source 107 is fixed at about one half of the current flowing through a cell which is in the ON state. Accordingly, the voltage of the reference signal at node N2 is maintained at a voltage midway between the voltage generated by reading a cell in the ON state and a cell in the OFF state.
The operation of the sense amplifier of FIG. 1 will now be described in more detail with reference to FIG. 2 which shows variations in the voltages at the references node N2 and the sense node N20. The PMOS current supply transistor 104 of reference signal generator 100 is diode connected in a feedback configuration in which its gate is connected to its drain at node N2. In this configuration it serves as a current supply source for current which is discharged from node N2 by the reference cell current supply source 107. Similarly, PMOS current supply transistor 204 of the sense signal generator 200 is diode connected in a feedback configuration in which its gate is connected to its drain at the sense node N20 from which the memory cell current supply source 207 discharges current.
When the current supply transistors 102 and 104 are diode connected in feedback configurations, the sense amplifier operates as follows during a read operation.
When the memory cell is in an OFF state, PMOS transistor 204 continuously supplies current to the sense node N20. This causes the voltage at node N20 to increase rapidly because the memory cell current source 207 does not discharge any current from node N20 when it is in the OFF state. However, when the voltage at node N20 rises to a certain level, PMOS transistor 204 switches off due to the voltage on its gate. Thus, the voltage at node N20 is limited before a sense operation begins. On the other hand, when the memory cell is in the ON state, the voltage at node N20 decreases rapidly. However, when the voltage at node N20 decreases to a certain level, PMOS transistor 204 switches on, thereby limiting the level to which the voltage at node N20 can drop.
Thus, when the current source transistors 104 and 204 in the reference signal generator and sense signal generator are diode connected in a feedback configuration, the differential voltage between the reference node N2 and the sense node N20 is limited by the feedback operation of transistors 104 and 204. However, the differential voltage between the reference node N2 and sense node N20 must be increased to increase the sensing speed and sensitivity of differential amplifier 300. Thus, the feedback connected transistors 102 and 104 limit the speed and sensitivity of the sense amplifier.